In accordance with the International Technology Roadmap for Semiconductors (ITRS), technology nodes below 40 nm have fixed polysilicon (poly) patterns having fixed pitches or uni-direction poly patterns for the manufacturing of metal oxide semiconductor (MOS) devices. These fixed poly pitch patterns for technology nodes smaller than 40 nm preclude large continuous lengths of poly. This restraint on large poly width dimensions is problematic in many analog circuits based on MOS devices, which require large gate-source resistances for providing large gains.
Accordingly, an improved design for MOS devices is desirable.